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1 features ? 1.65v - 1.95v read/write high performance ? random access time ? 70 ns ? page mode read time ? 20 ns ? synchronous burst frequency ? 66 mhz ? configurable burst operation sector erase architecture ? sixteen 4k word sectors with individual write lockout ? two hundred fifty-four 32k word main sectors with individual write lockout typical sector erase time: 32k word sectors ? 500 ms; 4k word sectors ? 100 ms thirty-two plane organization, permitting concurrent read in any of the thirty-one planes not being programmed/erased suspend/resume feature for erase and program ? supports reading and programming data from any sector by suspending erase of a different sector ? supports reading any word by suspending programming of any other word low-power operation ?30 ma active ? 10 a standby vpp pin for write protection and accelerated program/erase operations reset input for device initialization cbga and tsop packages seventeen 128-bit protection registers (2,176 bits) common flash interface (cfi) description the at49sn/sv12804 is a 1.8-volt 128-megabit flash memory. the memory is divided into multiple sectors and planes for erase operations. the at49sn/sv12804 is organized as 8,388,608 x 16 bits. the device can be read or reprogrammed off a single 1.8v power supply, making it ideally suited for in-system programming. the device can be configured to operate in the asynchronous/page read (default mode) or burst read mode (not available for the AT49SV12804). the burst read mode is used to achieve a faster data rate than is possible in the asynchronous/page read mode. if the avd and the clk signals are both tied to gnd and the burst configuration register is configured to perform asynchronous reads, the device will behave like a standard asynchronous flash memory. in the page mode, the avd signal can be tied to gnd or can be pulsed low to latch the page address. in both cases the clk can be tied to gnd. the at49sn/sv12804 is divided into thirty-two memory planes. a read operation can occur in any of the thirty-one planes which is not being programmed or erased. this concurrent operation allows improved system performance by not requiring the sys- tem to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend and pro- gram suspend feature. this feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remain- ing sectors. there is no reason to suspend the erase or program operation if the data to be read is in another memory plane. the vpp pin provides data protection and faster programming and erase times. when the v pp input is below 0.4v, the program and erase functions are inhibited. when v pp is at 0.9v or above, normal program and erase operations can be performed. with v pp at 12.0v, the program (dual-word program command) and erase operations are accelerated. 128-megabit (8m x 16) burst/page mode 1.8-volt flash memory at49sn12804 AT49SV12804 preliminary rev. 3314a?flash?4/04
2 at49sn/sv12804 [preliminary] 3314a?flash?4/04 at49sn/sv12804: pin configurations note: 1. these signals are not available for use with the AT49SV12804. the AT49SV12804 can only be used in the asynchro- nous/page mode. pin name pin function i/o0 - i/o15 data inputs/outputs a0 - a22 addresses ce chip enable oe output enable we write enable avd (1) address latch enable clk (1) clock reset reset wp (1) write protect vpp write protection and power supply for accelerated program operations wait (1) wait vccq output power supply at49sn12804: cbga ? top view a b c d e f g 1 2345678 a11 a12 a13 a15 vccq vss i/o7 a8 a9 a10 a14 i/o15 i/o14 vss vss a20 a21 wait i/o6 i/013 i/o5 vcc clk avd a16 i/o4 i/o11 vcc vpp reset we i/o12 i/o2 i/o10 i/o3 a18 a17 a19 wp i/o1 i/o9 vccq a6 a5 a7 a22 ce i/o0 i/o8 a4 a3 a2 a1 a0 oe vss AT49SV12804: tsop ? top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a21 nc a20 a19 a18 a17 a16 a15 vcc a14 a13 a12 a11 ce vpp rst a10 a9 a8 a7 vss a6 a5 a4 a3 a2 a1 a0 nc we oe nc i/o15 i/o7 i/o14 i/o6 vss i/o13 i/o5 i/o12 i/o4 vccq vss i/o11 i/o3 i/o10 i/o2 vcc i/o9 i/o1 i/o8 i/o0 nc nc a22 nc
3 at49sn/sv12804 [preliminary] 3314a?flash?4/04 device operation command sequences: when the device is first power ed on, it will be in the read mode. command sequences are used to place the device in other operating modes such as program and erase. the command sequences are written by applying a low pulse on the we input with ce low and oe high or by applying a low-going pulse on the ce input with we low and oe high. prior to the low-going pulse on the ce or we signal, the address input may be latched by a low-to-high transition on the avd signal. if the avd is not pulsed low, the address will be latched on the first rising edge of the we or ce . valid data is latched on the rising edge of the we or the ce pulse, whichever occurs first. the addresses used in the command sequences are not affected by entering the command sequences. burst configuration command: the program burst configuration register command is used to program the burst configuration register. the burst configuration register determines several parameters that control the read operation of the device. bit b15 determines whether synchronous burst reads are enabled or asynchronous reads are enabled. since the page read operation is an asynchronous operation, bit b15 must be set for asynchronous reads to enable the page read feature. bit b14 determines whether a four-word page or an eight-word page will be used. the rest of the bits in the burst configuration register are used only for the burst read mode. bits b13 - b11 of the burst configuration register determine the clock latency for the burst mode. the latency can be set to two, three, four, five or six cycles. the clock latency versus input clock frequency table is shown on page 20. the ?burst read waveform? as shown on page 31 illustrates a clock latency of four; the data is output from the device four clock cycles after the first valid clock edge following the high-to-low avd edge. the b10 bit of the configuration register determines the polarit y of the wait signal. the b9 bit of the burst configuration register determines the number of clocks that data will be held valid (see figure 4). the hold data for 2 clock cycles read waveform is shown on page 31. the clock latency is not affected by the value of the b9 bit. the b8 bit of the burst configuration register deter- mines when the wait signal will be asserted. when synchronous burst reads are enabled, a linear burst sequence is selected by setting bit b7. bit b6 selects whether the burst starts and the data output will be relative to the falling edge or the rising edge of the clock. bits b2 - b0 of the burst configuration register determine whether a continuous or fixed-length burst will be used and also determine whether a four-, eight - or sixteen-word length will be used in the fixed-length mode. when a four-, eight- or sixteen-word burst length is selected, bit b3 can be used to select whether burst accesses wrap within the burst length boundary or whether they cross word length boundaries to perform linear accesses (see table 5). all other bits in the burst configuration register should be programmed as shown on page 20. the default state (after power-up or reset) of the burst configuration register is also shown on page 20. asynchronous read: there are two types of asynchronous reads ? avd pulsed and standard asynchronous reads. the avd pulsed read operation of the device is controlled by ce , oe , and avd inputs. the outputs are put in the high-impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. the data at the address location defined by a0 - a22 and captured by the avd signal will be read when ce and oe are low. the address location passes into the device when ce and avd are low; the address is latched on the low-to-high transition of avd . low input levels on the oe and ce pins allow the data to be driven out of the devic e. the access time is measured from stable address, falling edge of avd or falling edge of ce , whichever occurs last. during the avd pulsed read, the clk signal may be static high or static low. for standard asynchronous reads, the avd and clk signal should be tied to gnd. the asynchronous read diagrams are shown on page 28. page read: the page read operation of the device is controlled by ce , oe , and avd inputs. the clk input is ignored during a page read operation and should be tied to gnd. the page size can be four words (default value) or eight words depending on what value bit b14 of the burst configuration register is programmed to. during a page read, the avd signal can transi- tion low and then transition high, transition low and remain low, or can be tied to gnd. if a high to low transition on the avd signal occurs, as shown in page read cycle waveform 1, the
4 at49sn/sv12804 [preliminary] 3314a?flash?4/04 page address is latched by the low-to-high transition of the avd signal. however, if the avd signal remains low after the high-to-low transition or if the avd signal is tied to gnd, as shown in page read cycle waveform 2, then the page address (determined by a22 - a3 for an eight word page and a22 - a2 for a four-word page) cannot change during a page read operation. the first word access of the page read is the same as the asynchronous read. the first word is read at an asynchronous speed of 90 ns. once the first word is read, toggling a0 and a1 (four- word page mode) or toggling a0, a1, and a2 (eight word page mode) will result in subsequent reads within the page being output at a speed of 20 ns. if the avd and the clk pins are both tied to gnd, the device will behave like a standard asynchronous flash memory. the page read diagrams are shown on page 22. synchronous reads: synchronous reads (not available on the AT49SV12804) are used to achieve a faster data rate that is possible in the asynchronous/page read mode. the device can be configured for continuous or fixed-length burst access. the burst read operation of the device is controlled by ce , oe , clk and avd inputs. the initial read location is determined as for the avd pulsed asynchronous read operation; it can be any memory location in the device. in the burst access, the address is latched on the rising edge of the first clock pulse when avd is low or the rising edge of the avd signal, whichever occurs first. the clk input signal con- trols the flow of data from the device for a burst operation. after the clock latency cycles, the data at the next burst address location is read for each following clock cycle. figure 1. word boundary continuous burst read : during a continuous burst read, any number of addresses can be read from the memory. when operating in the linear burst read mode (b7 = 1) with the burst wrap bit (b3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory (see figure 1). if the starting address is d0 - d12, there is no delay. if the starting address is d13 - d15, an output delay equal to the initial clock latency is incurred. the delay takes place only once, and only if the burst sequence crosses a 16-word boundary. to indicate that the device is not ready to con- tinue the burst, the device will drive the wait pin low (b10 and b8 = 0) during the clock cycles in which new data is not being presented. once the wait pin is driven high (b10 and b8 = 0), the current data will be valid. the wait signal will be tri-stated when the ce or oe signal is high. in the ?burst read waveform? as shown on page 31, the valid address is latched at point a. for the specified clock latency of three, data d13 is valid within 13 ns of clock edge b. the low-to-high transition of the clock at point c results in d14 being read. the transition of the clock at point d results in a burst read of d15. the clock transition at point e does not cause new data to appear on the output lines because the wait signal goes low (b10 and b8 = 0) after the clock transition, which signifies that the first boundary in the memory has been crossed and that new data is not available. after a clock latency of three, the clock transition at point f does cause a burst read of data d16 because the wait signal goes high (b10 and b8 = 0) after the clock transition indicating that new data is available. additional clock transitions, like at point g, will continue to result in burst reads. 16-word boundary word d0 - d3 word d4 - d7 word d8 - d11 word d12 - d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15
5 at49sn/sv12804 [preliminary] 3314a?flash?4/04 fixed-length burst reads: during a fixed-length burst mode read, four, eight or six- teen words of data may be burst from the device, depending upon the configuration. the device supports a linear burst mode. the burst sequence is shown on page 21. when operat- ing in the linear burst read mode (b7 = 1) with the burst wrap bit (b3 = 1) set, the device may incur an output delay when the burst sequence crosses the first 16-word boundary in the memory. if the starting is d0 - d12, there is no delay. if the starting address is d13 - d15, an output delay equal to the initial clock latency is incurred. the delay takes place only once, and only if the burst sequence crosses a 16-word boundary. to indicate that the device is not ready to continue the burst, the device will drive the wait pin low (b10 and b8 = 0) during the clock cycles in which new data is not being presented. once the wait pin is driven high (b10 and b8 = 0), the current data will be valid. the wait signal will be tri-stated when the ce or oe signal is high. the ?four-word burst read waveform? on page 32 illustrates a fixed-length burst cycle. the valid address is latched at point a. for the specified clock latency of four, data d0 is valid within 13 ns of clock edge b. the low-to-high transition of the clock at point c results in d1 being read. similarly, d2 and d3 are output following the next two clock cycles. returning ce high ends the read cycle. there is no output delay in the burst access wrap mode (b3 = 0). burst suspend: the burst suspend feature allows the system to temporarily suspend a synchronous burst operation if the system needs to use the flash address and data bus for other purposes. burst accesses can be suspended during the initial latency (before data is received) or after the device has output data. when a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. burst suspend occurs when ce is asserted, the current address has been latched (either ris- ing edge of avd or valid clk edge), clk is halted, and oe is deasserted. the clk can be halted when it is at v ih or v il . to resume the burst access, oe is reasserted and the clk is restarted. subsequent clk edges resume the burst sequence where it left off. within the device, oe gates the wait signal. therefore, during burst suspend the wait sig- nal reverts to a high-impedance state when oe is deasserted. see ?burst suspend waveform? on page 32. reset: a reset input pin is provided to ease some system applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. when a high level is reasserted on the reset pin, the device returns to read mode. erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical ?1?. the entire memory can be erased by using the chip erase com- mand or individual planes can be erased by using the plane erase command or individual sectors can be erased by using the sector erase command.
6 at49sn/sv12804 [preliminary] 3314a?flash?4/04 chip erase : chip erase is a two-bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. the hardware reset during chip erase will stop the erase, but the data will be of an unknown state. plane erase: as an alternative to a full chip erase, the device is organized into thirty-two planes that can be individually erased. the plane erase command is a two-bus cycle opera- tion. the plane whose address is valid at the second rising edge of we will be erased. the plane erase command does not alter the data in the protected sectors. sector erase: the device is organized into multiple sectors that can be individually erased. the sector erase command is a two-bus cycle operation. the sector whose address is valid at the second rising edge of we will be erased provided the given sector has not been protected. word programming: the device is programmed on a word-by-word basis. programming is accomplished via the internal device command register and is a two-bus cycle operation. the programming address and data are latched in the second cycle. the device will automati- cally generate the required internal programmi ng pulses. please note that a ?0? cannot be programmed back to a ?1?; only erase operations can convert ?0?s to ?1?s. flexible sector protection: the at49sn/sv12804 offers two sector protection modes, the softlock and the hardlock. the softlock mode is optimized as sector protection for sectors whose content changes frequently. the hardlock protection mode is recommended for sectors whose content changes infrequently. once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. each sector can be independently programmed for either the softlock or hardlock sector protection mode. at power-up and reset, all sectors have their softlock protection mode enabled. softlock and unlock: the softlock protection mode can be disabled by issuing a two- bus cycle unlock command to the selected sector. once a sector is unlocked, its contents can be erased or programmed. to enable the softlock protection mode, a two-bus cycle softlock command must be issued to the selected sector. hardlock and write protect (wp ): the hardlock sector protection mode operates in conjunction with the write protection (wp ) pin. the hardlock sector protection mode can be enabled by issuing a two-bus cycle hardlock software command to the selected sector. the state of the write protect pin affects whether the hardlock protection mode can be overridden. when the wp pin is low and the hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. when the wp pin is high, the hardlock protection mode is overridden and the sector can be unlocked via the unlock command.
7 at49sn/sv12804 [preliminary] 3314a?flash?4/04 to disable the hardlock sector protection mode, the chip must be either reset or power cycled. figure 2. sector locking state diagram note: 1. the notation [x, y, z] denotes the locking state of a sector. the current locking state of a sector is defined by the state of wp and the two bits of the sector-lock status d[1:0]. table 1. hardlock and softlock protection configurations in conjunction with wp v pp wp hard- lock soft- lock erase/ prog allowed? comments v cc 0 0 0 yes no sector is locked v cc 0 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc 0 1 1 no hardlock protection mode is enabled. the sector cannot be unlocked. v cc 1 0 0 yes no sector is locked. v cc 1 0 1 no sector is softlocked. the unlock command can unlock the sector. v cc 1 1 0 yes hardlock protection mode is overridden and the sector is not locked. v cc 1 1 1 no hardlock protection mode is overridden and the sector can be unlocked via the unlock command. v il x x x no erase and program operations cannot be performed. [000] [001] [011] [111] [101] [110] [100] unlocked locked wp = v il =0 wp = v ih =1 power-up/reset default power-up/reset default hardlocked is disabled by wp = v ih = unlock command = softlock command = hardlock command hardlocked ab c c ab ab c c a b c
8 at49sn/sv12804 [preliminary] 3314a?flash?4/04 sector protection detection: a software method is available to determine if the sec- tor protection softlock or hardlock features are enabled. when the device is in the software product identification mode a read from the i/o0 and i/o1 at address location 00002h within a sector will show if the sector is unlocked, softlocked, or hardlocked. read status register : the status register indicates the status of device operations and the success/failure of that operation. the read status register command causes subsequent reads to output data from the status register until another command is issued. to return to reading from the memory, issue a read command. the status register bits are output on i/o7 - i/o0. the upper byte, i/o15 - i/o8, outputs 00h when a read status register command is issued. the contents of the status register [sr7:sr0] are latched on the falling edge of oe or ce (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. ce or oe must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. when the write state machine (wsm) is active, sr7 will indicate the status of the wsm; the remaining bits in the status register indicate whether the wsm was successful in performing the preferred operation (see table 3). table 2. sector protection status i/o1 i/o0 sector protection status 0 0 sector not locked 0 1 softlock enabled 1 0 hardlock enabled 1 1 both hardlock and softlock enabled
9 at49sn/sv12804 [preliminary] 3314a?flash?4/04 read status register in the burst mode: the waveform below shows a status register read during a program operation. the two-bus cycle command for a program opera- tion is given followed by a read status regist er command. following the read status register command, the avd signal is pulsed low to latch the valid address at point a. with the oe sig- nal pulsed low and for the specified clock latency of three, the status register output is valid within 13 ns from clock edge b. the same status register data is output on successive clock edges. to update the status register output, the avd signal needs to be pulsed low and the next data is available after a clock latency of three. the status register output is also available after the chosen clock latency during an erase operation. figure 3. read status register in the burst mode note: 1. the wait signal is for a burst configuration setting of b10 and b8 = 0. xx 40h/10h data 70h 00h 80h address ce a0 - a22 i/o0 - i/o15 avd clk oe we wait (1) b a
10 at49sn/sv12804 [preliminary] 3314a?flash?4/04 note: 1. a command sequence error is indicated when sr1, sr3, sr4 and sr5 are set. table 3. status register bit definition wsms ess es prs vpps pss sls pls 76543210 notes sr7 write state machine status (wsms) 1 = ready 0 = busy check write state machine bit first to determine word program or sector erase completion, before checking program or erase status bits. sr6 = erase suspend status (ess) 1 = erase suspended 0 = erase in progress/completed when erase suspend is issued, wsm halts execution and sets both wsms and ess bits to ?1? ? ess bit remains set to ?1? until an erase resume command is issued. sr5 = erase status (es) 1 = error in sector erase 0 = successful sector erase when this bit is set to ?1?, wsm has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure. sr4 = program status (prs) 1 = error in programming 0 = successful programming when this bit is set to ?1?, wsm has attempted but failed to program a word sr3 = vpp status (vpps) 1 = vpp low detect, operation abort 0 = vpp ok the v pp status bit does not provide continuous indication of vpp level. the wsm interrogates v pp level only after the program or erase command sequences have been entered and informs the system if v pp has not been switched on. the v pp is also checked before the operation is verified by the wsm. sr2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed when program suspend is issued, wsm halts execution and sets both wsms and pss bits to ?1?. pss bit remains set to ?1? until a program resume command is issued. sr1 = sector lock status 1 = prog/erase attempted on a locked sector; operation aborted. 0 = no operation to locked sectors if a program or erase operation is attempted to one of the locked sectors, this bit is set by the wsm. the operation specified is aborted and the device is returned to read status mode. sr0 = plane status (pls) indicates program or erase status of the addressed plane. table 4. status register device wsms and write status definition wsms (sr7) pls (sr0) description 0 0 the addressed plane is performing a program/erase operation. 0 1 a plane other than the one currently addressed is performing a program/erase operation. 1 x no program/erase operation is in progress in any plane. erase and program suspend bits (sr6, sr2) indicate whether other planes are suspended.
11 at49sn/sv12804 [preliminary] 3314a?flash?4/04 erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector erase or plane erase operation. the erase suspend command does not work with the chip erase feature. using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. since this device is organized into thirty-two planes, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. after the erase suspend command is given, the device requires a maximum time of 15 s to sus- pend the erase operation. after the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one-bus cycle command, which does require the plane address. read, read status register, product id entry, clear status register, pro- gram, program suspend, erase resume, sector softlock/hardlock, sector unlock are valid commands during an erase suspend. program suspend/program resume: the program suspend command allows the system to interrupt a programming operation a nd then read data from a different word within the memory. after the program suspend command is given, the device requires a maximum of 10 s to suspend the programming operati on. after the programming operation has been suspended, the system can then read from any other word within the device. an address is not required during the program suspend operation. to resume the programming operation, the system must write the program resume command. the program suspend and resume are one-bus cycle commands. the command sequence for the erase suspend and program sus- pend are the same, and the command sequence for the erase resume and program resume are the same. read, read status register, product id entry, program resume are valid com- mands during a program suspend. 128-bit protection registers: the at49sn/sv12804 contains seventeen (pr0 - pr16) 128-bit registers that can be used for security purposes in system design. please see the protection register addressing table on page 19 for the address locations within each protection register. the first protection register (pr0) is divided into two 64-bit blocks. the two blocks are designated as block a and block b. the data in block a is non-changeable and is programmed at the factory with a unique number. the data in block b is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. the other 16 registers (pr1 - pr16) have 128 bits (16 words) each that are all user programmable. to pro- gram block b in pr0 or to program pr1 - pr16 register, a two-bus cycle command must be used as shown in the command definition table on page 18. to lock out block b in pro or to lock out pr1 - pr16, a two-bus cycle command must also be used as shown in the command definition table. to lock out block b in pro, the address used in the second bus cycle is 080h and data bit d1 must be zero during the second bus cycle. all other data bits during the sec- ond bus cycle are don?t cares. to lock out pr1 - pr16, the address used in the second bus cycle is 089h and sixteen bits of data are programmed. if any of these bits is programmed to a zero, the appropriate register is locked. after being locked, the protection register cannot be unlocked. to determine whether block b in pro or pr1 - pr16 is locked out, the product id entry command is given followed by a read operation from address 80h or address 89h, respectively. (this command is shown as status of protection in the command definition table). for block b in pro, if data bit d1 is zero, block b is locked. if data bit d1 is one, block b can be reprogrammed. for pr1 - pr16, sixteen bits of data are read out. each bit represents the protection status of a particular register. if the bit is a zero, the register is locked. if the bit is a one, the register can be reprogrammed. to read a protection register, the product id entry command is given followed by a normal read operation from an address within the protection register. after determining whether a register is protected or not or reading the protection reg- ister, the read command must be given to return to the read mode.
12 at49sn/sv12804 [preliminary] 3314a?flash?4/04 cfi: common flash interface (cfi) is a published, standardized data structure that may be read from a flash device. cfi allows system software to query the installed device to deter- mine the configurations, various electrical and timing parameters, and functions supported by the device. cfi is used to allow the system to learn how to interface to the flash device most optimally. the two primary benefits of using cfi are ease of upgrading and second source availability. the command to enter the cfi query mode is a one-bus cycle command which requires writing data 98h to any address. the cfi query command can be written when the device is ready to read data or can also be wr itten when the part is in the product id mode. once in the cfi query mode, the system can read cfi data at the addresses given in table on page 31. to return to the read mode, the read command should be issued. hardware data protection: hardware features protect against inadvertent programs to the at49sn/sv12804 in the following ways: (a) v cc sense: if v cc is below 1.2v (typical), the device is reset and the program and erase functions are inhibited. (b) v cc power-on delay: once v cc has reached the v cc sense level, the device will automatically time-out 10 ms (typi- cal) before programming. (c) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. (e) v pp is less than v ilpp . input levels: while operating with a 1.65v to 1.95v power supply, the address inputs and control inputs (oe , ce and we ) may be driven from 0 to 2.5v without adversely affecting the operation of the device. the i/o lines can be driven from 0 to v ccq + 0.6v. output levels: for the at49sn/sv12804, output high levels are equal to v ccq - 0.1v (not v cc ). v ccq must be regulated between 1.8v - 2.25v.
13 at49sn/sv12804 [preliminary] 3314a?flash?4/04 word program flowchart full status check flowchart pr ogram suspend loop start wr ite 40, wor d addr ess wr ite d ata, wor d addr ess read status register sr 7 = full status check (if desired) progr am complete suspend? 1 0 no yes (s etup) (confirm) read status register progr am successful sr3 = sr1 = 0 0 sr4 = 0 1 1 1 v pp range error device pr otect err or progr am error word program procedure full status check procedure bus operation command comments write program setup data = 40 addr = location to program write data data = data to program addr = location to program read none status register data: toggle ce or oe to update status register idle none check sr7 1 = wsm ready 0 = wsm busy repeat for subsequent word program operations. full status register check can be done after each program, or after a sequence of program operations. write ff after the last operation to set to the read state. bus operation command comments idle none check sr3: 1 = v pp error idle none check sr4: 1 = data program error idle none check sr1: 1 = sector locked; operation aborted sr3 must be cleared before the write state machine allows further program attempts. if an error is detected, clear the status register before continuing operations ? only the clear status register command clears the status register error bits.
14 at49sn/sv12804 [preliminary] 3314a?flash?4/04 program suspend/resume flowchart r ead status register sr7 = sr2 = read data program completed done reading program resumed read data 0 no 0 yes 1 1 wr ite ff (read array) wr ite d 0 any address (program resume) wr ite ff (read array) start wr ite b0 any address (program suspend) wr ite 70 any address (read status) the same plane within suspend plane write 70h any address within the same plane (read status) program suspend/re sume procedure bus operation command comments write program suspend data = b0 addr = sector address to suspend (sa) write read status data = 70 addr = any address within the same plane read none status register data: toggle ce or oe to update status register addr = any address idle none check sr7 1 = wsm ready 0 = wsm busy idle none check sr2 1 = program suspended 0 = program completed write read array data = ff addr = any address within the suspended plane read none read data from any sector in the memory other than the one being programmed write program resume data = d0 addr = any address if the suspend plane was placed in read mode: write read status return plane to status mode: data = 70 addr = any address within the same plane
15 at49sn/sv12804 [preliminary] 3314a?flash?4/04 erase suspend/resume flowchart erase completed read array data 0 0 1 1 start read status r egister sr7 = sr6 = er ase resumed done? r ead read or program? wr ite 70, any addr ess (read status) wr ite b 0, any addr ess (erase suspend) wr ite d 0, any addr ess (e rase re sum e) wri te ff (read a rray) no yes program loop write 70h any address within the same plane (read status) erase suspend/resume procedure bus operation command comments write erase suspend data = b0 addr = any address within the same plane write read status data = 70 addr = any address read none status register data: toggle ce or oe to update status register addr = any address within the same plane idle none check sr7 1 = wsm ready 0 = wsm busy idle none check sr6 1 = erase suspended 0 = erase completed write read or program data = ff or 40 addr = any address read or write none read or program data from/to sector other than the one being erased write program resume data = d0 addr = any address if the suspended plane was placed in read mode or a program loop: write read status return plane to status mode: data = 70 addr = any address within the same plane
16 at49sn/sv12804 [preliminary] 3314a?flash?4/04 sector erase flowchart full erase status check flowchart start no suspend erase 1 0 yes suspend erase loop write 2 0, addr ess write d0, addr ess read status r egister sr7 = full erase status check (if desired) erase complete (erase) (erase confirm) sector sector sector sector 0 0 0 1 1,1 1 1 0 read status r egister erase successful sr1 = sector sector locked error sr3 = v pp range error sr4, sr5 = command sequence er r or sr5 = erase error sector sector erase procedure full erase status check procedure bus operation command comments write sector erase setup data = 20 addr = sector to be erased (sa) write erase confirm data = d0 addr = sector to be erased (sa) read none status register data: toggle ce or oe to update status register data idle none check sr7 1 = wsms ready 0 = wsms busy repeat for subsequent sector erasures. full status register check can be done after each sector erase, or after a sequence of sector erasures. write ff after the last operation to enter read mode. bus operation command comments idle none check sr3: 1 = v pp range error idle none check sr4, sr5: both 1 = command sequence error idle none check sr5: 1 = sector erase error idle none check sr1: 1 = attempted erase of locked sector; erase aborted. sr1, sr3 must be cleared before the write state machine allows further erase attempts. only the clear status register command clears sr1, sr3, sr4, sr5. if an error is detected, clear the status register before attempting an erase retry or other error recovery.
17 at49sn/sv12804 [preliminary] 3314a?flash?4/04 protection register programming flowchart full status check flowchart 1 0 start write c0, pr address write pr address & data read status register sr7 = full status check (if desir ed) pr ogram complete (program setup) (confirm data) 0, 1 1, 1 read status register data pr ogram successful = v pp range error program er ror register locked; program aborted 0 0 sr1, sr4 sr1, sr4 sr3, sr4 = 0 = 1, 1 protection register programming procedure full status check procedure bus operation command comments write program pr setup data = c0 addr = first location to program write protection program data = data to program addr = location to program read none status register data: toggle ce or oe to update status register data idle none check sr7 1 = wsms ready 0 = wsms busy program protection register operation addresses must be within the protection register address space. addresses outside this space will return an error. repeat for subsequent programming operations. full status register check can be done after each program, or after a sequence of program operations. write ff after the last operation to return to the read mode. bus operation command comments idle none check sr1, sr3, sr4: 0,1,1 = v pp range error idle none check sr1, sr3, sr4: 0,0,1 = programming error idle none check sr1, sr3, sr4: 1, 0,1 = sector locked; operation aborted sr3 must be cleared before the write state machine allows further program attempts. only the clear status register command clears sr1, sr3, sr4. if an error is detected, clear the status register before attempting a program retry or other error recovery.
18 at49sn/sv12804 [preliminary] 3314a?flash?4/04 notes: 1. the data format shown for each bus cycle is as follows; i/o7 - i/o0 (hex). i/o15 - i/o8 are don?t care. the address for mat shown for each bus cycle is as follows: a7 - a0 (hex). address a22 through a8 are don?t care. 2. pa is the plane address (a22 - a18). any address within a plane can be used. 3. sa = sector address. any word address within a sector can be used to designate the sector address (see pages 22 - 25 for deta ils). 4. the status register bits are output on i/o7 - i/o0. 5. if data bit d1 is ?0?, block b is locked. if data bit d1 is ?1?, block b can be reprogrammed. 6. see ?burst configuration register? on page 20. bits b15 - b0 of the burst configuration register determine a15 - a0. addresse s a16 - a22 can select any plane. 7. the plane address has to be the same as the plane address in the second bus cycle. 8. any address within the user programmable protection register region. 9. this fast programming option enables the user to program two words in parallel only when v pp = 12v. the addresses, addr0 and addr1, of the two words, d in0 and d in1 , must only differ in address a0. this command should be used during manufacturing purposes only. 10. address locations are shown on next page. 11. d in represents 16 bits of data. if any bit is programmed to a ?0?, the appropriate protection register is locked. 12. d out represents 16 bits of data. each bit corresponds to the protec tion status of a given register. the most significant bit read o ut corre- sponds to pr16, and the last significant bit corresponds to pr0. if the data bit is a ?0?, the register is locked. if the data bits is a ?1?, the register can be programmed. 13. the manufacturer code is read from address 0000h , and the device code is read from address 0001h. 14. the first bus cycle address should be the same as the word address to be programmed. command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle addr data addr data addr data read 1 pa (2) ff chip erase 2 xx 21 addr d0 plane erase 2 xx 22 addr d0 sector erase 2 sa 20 sa (3) d0 word program 2 addr (14) 40/10 addr (14) d in dual word program (9) 3 addr0 e0 addr0 d in0 addr1 d in1 erase/program suspend 1 xx b0 erase/program resume 1 pa d0 product id entry (13) 1pa90 sector softlock 2 sa 60 sa (3) 01 sector hardlock 2 sa 60 sa (3) 2f sector unlock 2 sa 60 sa (3) d0 read status register 2 pa 70 xx d out (4) clear status register 1 xx 50 program pr0 (block b) or pr1-pr16 2 xx (8) c0 addr (10) d in lock protection pr0 ? block b 2 80 c0 80 fffd lock protection pr1-pr16 2 xx c0 89 d in (11) status of protection pr0 (block b) 2 pa 90 80 d out (5) status of protection pr1-pr16 2 pa 90 89 d out (12) program burst configuration register 2 addr (6) 60 addr (6) 03 read burst configuration register 2 pa 90 pax005 (7) d out cfi query 1 xx 98
19 at49sn/sv12804 [preliminary] 3314a?flash?4/04 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a22 - a9 = 0. absolute maximum ratings* temperature under bias ................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages except v pp (including nc pins) with respect to ground ...................................-0.6v to +6.25v v pp input voltage with respect to ground ......................................... 0v to 12.5v all output voltages with respect to ground ...........................-0.6v to v ccq + 0.6v protection register addressing table addressuseblocka8a7a6a5a4a3a2a1a0 81factorya 010000001 82factorya 010000010 83factorya 010000011 pro 84factorya 010000100 85userb 010000101 86userb 010000110 87userb 010000111 88userb 010001000 8auser 010001010 pr1 ? ? ? ? ? ? 91user 010010001 92user 010010010 pr2 ? ? ? ? ? ? a1user 010100001 ? ? ? ? ? ? ? ? ? 102user 100000010 pr16 ? ? ? ? ? ? 109user 100001001
20 at49sn/sv12804 [preliminary] 3314a?flash?4/04 notes: 1. default state 2. burst configuration setting of b13 - b11 = 010 (clock latency of two), b9 = 1 (hold data for two clock cycles) and b8 = 1 (wa it asserted one clock cycle before data is valid) is not supported. 3. data is not ready when wait is asserted. figure 4. output configuration burst configuration register b15 0 1 (1) synchronous burst reads enabled asynchronous reads enabled b14 0 (1) 1 four-word page eight-word page b13 - b11: 010 (2) 011 100 101 110 (1) clock latency of two clock latency of three clock latency of four clock latency of five clock latency of six b10 0 1 (1)(3) wait signal is asserted low wait signal is asserted high b9 0 1 (1) hold data for one clock hold data for two clocks b8 0 1 (1) wait asserted during clock cycle in which data is valid wait asserted one clock cycle before data is valid b7 1 (1) linear burst sequence b6 0 1 (1) burst starts and data output on falling clock edge burst starts and data output on rising clock edge b5 - b4 00 (1) reserved for future use b3 0 1 (1) wrap burst within burst length set by b2 - b0 don?t wrap accesses within burst length set by b2 - b0 b2 - b0 001 010 011 111 (1) four-word burst eight-word burst sixteen-word burst continuous burst clock latency versus input clock frequency minimum clock latency (minimum number of clocks following address latch) input clock frequency 5, 6 66 mhz 4 61 mhz 2, 3 40 mhz valid output valid output valid output valid output valid output clk i/00 - i/015 i/00 - i/015 1 clk data hold (b9 = 0) 2 clk data hold (b9 = 1)
21 at49sn/sv12804 [preliminary] 3314a?flash?4/04 table 5. sequence and burst length start addr. (decimal) wrap b3 = 0 wrap b3 = 1 burst addressing sequence (decimal) 4-word burst length b2 ? b0 = 001 8-word burst length b2 ? b0 = 010 16-word burst length b2 ? b0 = 011 continuous burst b2 ? b0 = 111 linear linear linear linear 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6... 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3...14-15-0 1-2-3-4-5-6-7... 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4...15-0-1 2-3-4-5-6-7-8... 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5...15-0-1-2 3-4-5-6-7-8-9... 4 0 4-5-6-7-0-1-2-3 4-5-6...15-0-1-2-3 4-5-6-7-8-9-10... 5 0 5-6-7-0-1-2-3-4 5-6-7...15-0-1...4 5-6-7-8-9-10-11... 6 0 6-7-0-1-2-3-4-5 6-7-8...15-0-1...5 6-7-8-9-10-11-12... 7 0 7-0-1-2-3-4-5-6 7-8-9...15-0-1...6 7-8-9-10-11-12-13... ... ... ... ... ... ... ... 14 0 14-15-0-1...13 14-15-16-17-18-19-20 15 0 15-0-1-2-3...14 15-16-17-18-19-20-21 ... ... ... ... ... ... ... 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2...14-15 0-1-2-3-4-5-6... 1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3...15-16 1-2-3-4-5-6-7... 2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4...16-17 2-3-4-5-6-7-8... 3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5...17-18 3-4-5-6-7-8-9... 4 1 4-5-6-7-8-9-10-11 4-5-6...18-19 4-5-6-7-8-9-10... 5 1 5-6-7-8-9-10-11-12 5-6-7...19-20 5-6-7-8-9-10-11... 6 1 6-7-8-9-10-11-12-13 6-7-8...20-21 6-7-8-9-10-11-12... 7 1 7-8-9-10-11-12-13-14 7-8-9...21-22 7-8-9-10-11-12-13... ... ... ... ... ... ... ... 14 1 14-15...28-29 14-15-16-17-18-19-20 15 1 15-16...29-30 15-16-17-18-19-20-21
22 at49sn/sv12804 [preliminary] 3314a?flash?4/04 memory organization ? at49sn/sv12804 plane plane size (bits) sector size words x16 address range (a22 - a0) 1 4m sa0 4k 00000 - 00fff sa1 4k 01000 - 01fff sa2 4k 02000 - 02fff sa3 4k 03000 - 03fff sa4 4k 04000 - 04fff sa5 4k 05000 - 05fff sa6 4k 06000 - 06fff sa7 4k 07000 - 07fff sa8 32k 08000 - 0ffff sa9 32k 10000 - 17fff ? ? ? ? ? ? ? ? ? ? ? ? 1 sa13 32k 30000 - 37fff sa14 32k 38000 -3ffff 2 4m sa15 32k 40000 - 47fff ? ? ? ? ? ? ? ? ? ? ? ? 2 sa22 32k 78000 - 7ffff 3 4m sa23 32k 80000 - 87fff ? ? ? ? ? ? ? ? ? ? ? ? 3 sa30 32k b8000 - bffff 4 4m sa31 32k c0000 - c7fff ? ? ? ? ? ? ? ? ? ? ? ? 4 sa38 32k f8000 - fffff 5 4m sa39 32k 100000 - 107fff ? ? ? ? ? ? ? ? ? ? ? ? 5 sa46 32k 138000 - 13ffff 6 4m sa47 32k 140000 - 147fff ? ? ? ? ? ? ? ? ? ? ? ? 6 sa54 32k 178000 - 17ffff 7 4m sa55 32k 180000 - 187fff ? ? ? ? ? ? ? ? ? ? ? ? 7 sa62 32k 1b8000 - 1bffff
23 at49sn/sv12804 [preliminary] 3314a?flash?4/04 8 4m sa63 32k 1c0000 - 1c7fff ? ? ? ? ? ? ? ? ? ? ? ? 8 sa70 32k 1f8000 - 1fffff 9 4m sa71 32k 200000-207fff ? ? ? ? ? ? ? ? ? ? ? ? 9 sa78 32k 238000 - 23ffff 10 4m sa79 32k 240000 - 247fff ? ? ? ? ? ? ? ? ? ? ? ? 10 sa86 32k 278000 - 27ffff 11 4m sa87 32k 280000 - 287fff ? ? ? ? ? ? ? ? ? ? ? ? 11 sa94 32k 2b8000 - 2bffff 12 4m sa95 32k 2c0000 - 2c7fff ? ? ? ? ? ? ? ? ? ? ? ? 12 sa102 32k 2f8000 - 2fffff 13 4m sa103 32k 300000 - 307fff ? ? ? ? ? ? ? ? ? ? ? ? 13 sa110 32k 338000 - 33ffff 14 4m sa111 32k 340000 - 347fff ? ? ? ? ? ? ? ? ? ? ? ? 14 sa118 32k 378000 - 37ffff 15 4m sa119 32k 380000 - 387fff ? ? ? ? ? ? ? ? ? ? ? ? 15 sa126 32k 3b8000 - 3bffff 16 4m sa127 32k 3c0000 - 3c7fff ? ? ? ? ? ? ? ? ? ? ? ? 16 sa134 32k 3f8000 - 3fffff memory organization ? at49sn/sv12804 (continued) plane plane size (bits) sector size words x16 address range (a22 - a0)
24 at49sn/sv12804 [preliminary] 3314a?flash?4/04 17 4m sa135 32k 400000 - 407fff ? ? ? ? ? ? ? ? ? ? ? ? 17 sa142 32k 438000 - 43ffff 18 4m sa143 32k 440000 - 447fff ? ? ? ? ? ? ? ? ? ? ? ? 18 sa150 32k 478000 - 47ffff 19 4m sa151 32k 480000 - 487fff ? ? ? ? ? ? ? ? ? ? ? ? 19 sa158 32k 4b8000 - 4bffff 20 4m sa159 32k 4c0000 - 4c7fff ? ? ? ? ? ? ? ? ? ? ? ? 20 sa166 32k 4f8000 - 4fffff 21 4m sa167 32k 500000 - 507fff ? ? ? ? ? ? ? ? ? ? ? ? 21 sa174 32k 538000 - 53ffff 22 4m sa175 32k 540000 - 547fff ? ? ? ? ? ? ? ? ? ? ? ? 22 sa182 32k 578000 - 57ffff 23 4m sa183 32k 580000 - 587fff ? ? ? ? ? ? ? ? ? ? ? ? 23 sa190 32k 5b8000 - 5bffff 24 4m sa191 32k 5c0000 - 5c7fff ? ? ? ? ? ? ? ? ? ? ? ? 24 sa198 32k 5f8000 - 5fffff 25 4m sa199 32k 600000 - 607fff ? ? ? ? ? ? ? ? ? ? ? ? 25 sa206 32k 638000 - 63ffff memory organization ? at49sn/sv12804 (continued) plane plane size (bits) sector size words x16 address range (a22 - a0)
25 at49sn/sv12804 [preliminary] 3314a?flash?4/04 26 4m sa207 32k 640000 - 647fff ? ? ? ? ? ? ? ? ? ? ? ? 26 sa214 32k 678000 - 67ffff 27 4m sa215 32k 680000 - 687fff ? ? ? ? ? ? ? ? ? ? ? ? 27 sa222 32k 6b8000 - 6bffff 28 4m sa223 32k 6c0000 - 6c7fff ? ? ? ? ? ? ? ? ? ? ? ? 28 sa230 32k 6f8000 - 6fffff 29 4m sa231 32k 700000 - 707fff ? ? ? ? ? ? ? ? ? ? ? ? 29 sa238 32k 738000 - 73ffff 30 4m sa239 32k 740000 - 747fff ? ? ? ? ? ? ? ? ? ? ? ? 30 sa246 32k 778000 - 77ffff 31 4m sa247 32k 780000 - 787fff ? ? ? ? ? ? ? ? ? ? ? ? 31 sa254 32k 7b8000 - 7bffff 32 4m sa255 32k 7c0000 - 7c7fff sa256 32k 7c8000 - 7cffff ? ? ? ? ? ? ? ? ? ? ? ? 32 sa261 32k 7f0000 - 7f7fff sa262 4k 7f8000 - 7f8fff sa263 4k 7f9000 - 7f9fff sa264 4k 7fa000 - 7fafff sa265 4k 7fb000 - 7fbfff sa266 4k 7fc000 - 7fcfff sa267 4k 7fd000 - 7fdfff sa268 4k 7fe000 - 7fefff sa269 4k 7ff000 - 7fffff memory organization ? at49sn/sv12804 (continued) plane plane size (bits) sector size words x16 address range (a22 - a0)
26 at49sn/sv12804 [preliminary] 3314a?flash?4/04 notes: 1. x can be vil or vih. 2. refer to ac programming waveforms. 3. manufacturer code: 001fh; device code: 00bbh 4. the vpp pin can be tied to v cc . for faster program/erase operations, v pp can be set to 12.0v 0.5v. 5. v ihpp (min) = 0.9v. 6. v ilpp (max) = 0.4v. dc and ac operating range at49sn/sv12804-70 operating temperature (case) industrial -40c - 85c v cc power supply 1.65v - 1.95v operating modes mode ce oe we reset v pp (4) ai i/o read v il v il v ih v ih xai d out burst read v il v il v ih v ih xai d out program/erase (3) v il v ih v il v ih v ihpp (5) ai d in standby/program inhibit v ih x (1) xv ih x x high z program inhibit xxv ih v ih x xv il xv ih x xxx x v ilpp (6) output disable x v ih xv ih x high z reset x x x v il x x high z product identification software v ih a0 = v il , a1 - a22 = v il manufacturer code (3) a0 = v ih , a1 - a22 = v il device code (3)
27 at49sn/sv12804 [preliminary] 3314a?flash?4/04 note: 1. in the erase mode, i cc is 30 ma. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v i/o = 0v to v cc 1a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v cc 20 a i cc (1) v cc active current f = 66 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 66 mhz; i out = 0 ma 50 ma i ccrw v cc read while write current f = 66 mhz; i out = 0 ma 50 ma v il input low voltage 0.4 v v ih input high voltage v ccq - 0.2 v v ol output low voltage i ol = 100 a i ol = 2.1 ma 0.1 0.25 v v oh output high voltage i oh = -100 a v ccq - 0.1 v i oh = -400 a 1.4 ac driving levels 1.4v 0.4v 0.9v ac measurement level v 1.8k output pin 30 pf 1.3k ccq pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pf v in = 0v c out 812 pf v out = 0v
28 at49sn/sv12804 [preliminary] 3314a?flash?4/04 avd pulsed asynchronous read cycle waveform (1)(2) notes: 1. after the high-to-low transition on avd , avd may remain low as long as the address is stable. 2. clk may be static high or static low. asynchronous read cycle waveform (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (cl = 5 pf). 4. avd and clk should be tied low. ac asynchronous read timing characteristics symbol parameter min max units t acc1 access, avd to data valid 70 ns t acc2 access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t ahav address hold from avd 9ns t avlp avd low pulse width 10 ns t avhp avd high pulse width 10 ns t aav address valid to avd 7ns t df ce , oe high to data float 25 ns t oh output hold from oe , ce or address, whichever occurred first ns t ro reset to output delay 150 ns t ce t acc2 t df t df t ahav data valid ce i/o0-i/o15 a2 -a22 t aav t avlp t acc1 avd oe t oe t avhp reset t ro (1) t acc2 t ahav a0 -a1 t aav output valid i/o0 - i/o15 high z reset oe t oe t ce address valid t df t oh t acc2 t ro ce a0 - a22 t rc
29 at49sn/sv12804 [preliminary] 3314a?flash?4/04 page read cycle waveform 1 (1) note: 1. after the high-to-low transition on avd , avd may remain low as long as the page address is stable. page read cycle waveform 2 (1) note: 1. avd may remain low as long as the page address is stable. ac asynchronous read timing characteristics symbol parameter min max units t acc1 access, avd to data valid 70 ns t acc2 access, address to data valid 70 ns t ce access, ce to data valid 70 ns t oe oe to data valid 20 ns t ahav address hold from avd 9ns t avlp avd low pulse width 10 ns t avhp avd high pulse width 10 ns t aav address valid to avd 7ns t df ce , oe high to data float 25 ns t ro reset to output delay 150 ns t pa a page address access time 20 ns t ce t acc2 t df t df t ahav data va l i d ce i/o0-i/o15 a2 -a22 t aav t avlp t acc1 avd oe t oe t avhp reset t ro (1) t acc2 t ahav a0 -a1 t aav t pa a t ce t acc2 t df t df data va l i d ce i/o0-i/o15 a2 -a22 avd oe t oe reset t ro (1) t acc2 a0 -a1 t pa a v il
30 at49sn/sv12804 [preliminary] 3314a?flash?4/04 burst read cycle waveform notes: 1. the wait signal (dashed line) shown is for a burst configuration register setting of b10 and b8 = 0. the wait signal (s olid line) shown is for a burst configuration setting of b10 = 1 and b8 = 0. 2. after the high-to-low transition on avd , avd may remain low. ac burst read timing characteristics symbol parameter min max units t clk clk period 15 ns t ckh clk high time 4 ns t ckl clk low time 4 ns t ckrt clk rise time 3.5 ns t ckft clk fall time 3.5 ns t ack address valid to clock 7 ns t avck avd low to clock 7 ns t ceck ce low to clock 7 ns t ckav clock to avd high 3 ns t qhck output hold from clock 3 ns t ahck address hold from clock 8 ns t ckry clock to wait delay 13 ns t cesav ce setup to avd 10 ns t aav address valid to avd 10 ns t ahav address hold from avd 9ns t ckqv clk to data delay 13 ns t ceqz ce high to output high-z 10 ns d15 d13 d16 ce i/o0-i/o15 a0-a21 avd clk oe ... wait t cesav t ce t ahav t aav d17 ... d14 ... t ceck t ahck t avck t ack ... t ckav t ckry t ckry t clk t ckh t ckl t ckqv t ceqz t qhck (1) (2)
31 at49sn/sv12804 [preliminary] 3314a?flash?4/04 burst read waveform (clock latency of 3) note: 1. dashed line reflects a b10 and b8 setting of 0 in the configuration register. solid line reflects a b10 setting of 0 and b8 setting of 1 in the configuration register. hold data for 2 clock cycles read waveform (clock latency of 3) note: 1. dashed line reflects a burst configuration register setting of b10 and b8 = 0, b9 = 1. solid line reflects a burst configuration register setting of b10 = 0, b9 and b8 = 1 valid d13 d14 d15 ce a0-a21 i/o0-i/o15 avd clk oe wait (1) a c d e f g b high z high z d16 d18 d17 a0-a21 i/o0-i/o15 avd clk wait (1) oe ce d13 d14 d15 d16 a9
32 at49sn/sv12804 [preliminary] 3314a?flash?4/04 four-word burst read waveform (clock latency of 4) note: 1. the wait signal shown is for a burst configuration register of b10 and b8 = 1. burst suspend waveform notes: 1. the wait signal (dashed line) shown is for a burst configuration register setting of b10 and b8 = 0. the wait signal (s olid line) shown is for a burst configuration setting of b10 = 1 and b8 = 0. 2. during burst suspend, clk signal can be held low or high. ce a0-a21 i/o0-i/o15 avd clk oe valid a c b wait (1) high z high z d0 d2 d3 d1 d0 d1 d2 d1 ce i/o0-i/o15 a0-a21 avd clk oe t clk t ckh t ckl ... wait t ceav t ce t ahav t aav t ceck t ahck t avck t ack t ckav t ckqv t ceqz t qhck t df (2) (2) t oe
33 at49sn/sv12804 [preliminary] 3314a?flash?4/04 ac word load waveforms 1 we controlled (1) note: 1. after the high-to-low transition on avd , avd may remain low as long as the clk input does not toggle. ce controlled (1) note: 1. after the high-to-low transition on avd , avd may remain low as long as the clk input does not toggle. ac word load characteristics 1 symbol parameter min max units t aav address valid to avd high 10 ns t ahav address hold time from avd high 9 ns t avlp avd low pulse width 10 ns t ds data setup time 50 ns t dh data hold time 0 ns t cesav ce setup to avd 10 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns t weav we high time to avd low 25 ns t ceav ce high time to avd low 25 ns t ds t weav t dh t aav t ahav t avlp t wp data valid ce i/o0-i/o15 a0 -a22 avd we t ds t dh t ahav t avlp t wp data valid ce i/o0-i/o15 a0 -a22 avd we t cesav t ceav t aav
34 at49sn/sv12804 [preliminary] 3314a?flash?4/04 ac word load waveforms 2 we controlled (1) note: 1. the clk input should not toggle. ce controlled (1) note: 1. the clk input should not toggle. ac word load characteristics 2 symbol parameter min max units t as address setup time to we and ce high 50 ns t ah address hold time 0 ns t ds data setup time 50 ns t dh data hold time 0 ns t wp ce or we low pulse width 35 ns t wph ce or we high pulse width 25 ns i/o0 - i/o15 a0 - a22 we ce avd v il data valid i/o0 - i/o15 a0 - a22 ce avd v il data valid we
35 at49sn/sv12804 [preliminary] 3314a?flash?4/04 program cycle waveforms sector, plane or chip erase cycle waveforms notes: 1. any address can be used to load data. 2. oe must be high only when we and ce are both low. 3. the data can be 40h or 10h. 4. for chip erase, any address can be used. for plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. for chip erase, the data should be 21h, for plane erase, the data should be 22h, and for sector erase, the data should be 20h. program cycle characteristics symbol parameter min typ max units t bp word programming time 22 s t sec1 sector erase cycle time (4k word sectors) 200 ms t sec2 sector erase cycle time (32k word sectors) 700 ms t es erase suspend time 15 s t ps program suspend time 10 s t eres delay between erase resume and erase suspend 500 s oe program cycle input data note 3 address t bp t wp ce we avd a0 - a22 i/o0 - i/o15 t wph t as t ah t dh t ds t wc xx (1) v il oe (2) d0 xx (1) word 0 word 1 note 4 t wph t wp ce we a0 - a22 t as t ah t sec1/2 t dh t ds t wc avd i/o0 - i/o15 v il note 5
36 at49sn/sv12804 [preliminary] 3314a?flash?4/04 table 6. common flash interface definition for at49sn/sv12804 address at49sn/sv12804 comments 10h 0051h ?q? 11h 0052h ?r? 12h 0059h ?y? 13h 0003h 14h 0000h 15h 0041h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1ah 0000h 1bh 0016h vcc min write/erase 1ch 0019h vcc max write/erase 1dh 00b5h vpp min voltage 1eh 00c5h vpp max voltage 1fh 0004h typ word write ? 16 s 20h 0000h 21h 0009h typ block erase ? 500 ms 22h 0011h typ chip erase ? 131,000 ms 23h 0004h max word write/typ time 24h 0000h n/a 25h 0003h max block erase/typ block erase 26h 0003h max chip erase/ typ chip erase 27h 0018h device size 28h 0001h x16 device 29h 0000h x16 device 2ah 0000h multiple byte write not supported 2bh 0000h multiple byte write not supported 2ch 0003h 3 regions, x = 3 2dh 00fdh 64k bytes, y = 253 2eh 0000h 64k bytes, y = 253 2fh 0000h 64k bytes, z = 256 30h 0001h 64k bytes, z = 256 31h 0007h 8k bytes, y = 7 32h 0000h 8k bytes, y = 7 33h 0020h 8k bytes, z = 32 34h 0000h 8k bytes, z = 32 35h 0007h 8k bytes, y = 7 36h 0000h 8k bytes, y = 7 37h 0020h 8k bytes, z = 32 38h 0000h 8k bytes, z = 32
37 at49sn/sv12804 [preliminary] 3314a?flash?4/04 vendor specific extended query 41h 0050h ?p? 42h 0052h ?r? 43h 0049h ?i? 44h 0031h major version number, ascii 45h 0030h minor version number, ascii 46h 00bfh bit 0 ? chip erase supported, 0 ? no, 1 ? yes bit 1 ? erase suspend supported, 0 ? no, 1 ? yes bit 2 ? program suspend supported, 0 ? no, 1 ? yes bit 3 ? simultaneous operations supported, 0 ? no, 1 ? yes bit 4 ? burst mode read supported, 0 ? no, 1 ? yes bit 5 ? page mode read supported, 0 ? no, 1 ? yes bit 6 ? queued erase supported, 0 ? no, 1 ? yes bit 7 ? protection bits supported, 0 ? no, 1 ? yes 47h 0002h bit 8 ? top (?0?), bottom (?1?), or both top and bottom (?2?) boot block device undefined bits are ?0? 48h 000fh bit 0 ? 4 word linear burst with wrap around, 0 ? no, 1 ? yes bit 1 ? 8 word linear burst with wrap around, 0 ? no, 1 ? yes bit 2 ? 16 word linear burst with wrap around, 0 ? no, 1 ? yes bit 3 ? continuos burst, 0 ? no, 1 ? yes undefined bits are ?0? 49h 0003h bit 0 ? 4 word page, 0 ? no, 1 ? yes bit 1 ? 8 word page, 0 ? no, 1 ? yes undefined bits are ?0? 4ah 0080h location of protection register lock byte, the section?s first byte 4bh 0003h # of bytes in the factory prog section of prot register ? 2*n 4ch 0007h # of bytes in the user prog section of prot register ? 2*n ? 132 4dh 0020h number of planes ? 32 planes table 6. common flash interface definition for at49sn/sv12804 (continued) address at49sn/sv12804 comments
38 at49sn/sv12804 [preliminary] 3314a?flash?4/04 at49sn/sv12804 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 70 30 0.01 at49sn12804-70ci 56c3 industrial (-40 to 85 c) 70 30 0.01 AT49SV12804-70ti 56t industrial (-40 to 85 c) package type 56c3 56-ball, plastic chip-size ball grid array package (cbga) 56t 56-lead, plastic thin small outline package (tsop)
39 at49sn/sv12804 [preliminary] 3314a?flash?4/04 packaging information 56c3 ? cbga 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 56c3 , 56-ball (8 x 7 array), 8 x 10 x 1.0 mm body, 0.75 mm ball pitch ceramic ball grid array package (cbga) a 56c3 1/9/04 0.12 c seating plane c 1.375 mm ref d e top view side view a 87 6 5 4 3 21 ?b 2.75 mm ref bottom view a a1 d1 e1 e e b c d e f g common dimensions (unit of measure = mm) symbol min nom max note a ? ? 1.00 a1 0.21 ? ? d 7.90 8.00 8.10 d1 5.25 typ e 9.90 10.00 10.10 e1 4.50 typ e 0.75 typ ? b 0.35 typ
40 at49sn/sv12804 [preliminary] 3314a?flash?4/04 56t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 56t , 56-lead (14 x 20 mm package) plastic thin small outline package, type i (tsop) c 56t 10/23/03 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation ec. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.20 18.40 18.60 note 2 e 13.80 14.00 14.20 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.10 0.15 0.20 c 0.10 ? 0.21 e 0.50 basic
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